According to the functional requirements of the numerical control system, the task assignment of the upper computer and the lower computer, software and hardware is performed. The main tasks of the CPU software part of the host computer are to complete the rough interpolation operation of the contour, the speed control, the interpretation of the machining block, the user interface processing and the realization of the graphic simulation function. The main task of the hardware part is to realize the control of the D/A converter by using the parallel interface to control the spindle analog output; realize the data communication with the dual port RAM to transmit the data required for the FPGA fine interpolation; realize and control the chip CPLD Data communication with FPGA; realize interface with LCD screen; use communication interface to realize data communication with PC serial port; use GPIO port to realize control of keyboard scanning chip. The lower computer FPGA implements the following functions: a. Pulse generation module. The core module inside the FPGA divides the received clock signal to obtain the clock signal required to control the fine interpolation operation; reads the increment of each axis feed from the dual port RAM; and passes the fine interpolation DDA integrator The increment of each axis feed sent by the CPU is converted into a feed pulse signal and a feed direction signal for driving the motor.

b. Handwheel and encoder counting module. The 4 encoder return signals and the handwheel clockwise and counterclockwise rotation counts are counted in real time, and the count value is output for the CPU to read and calculate. cI/O control module. Through the module, the CPU can read the state level of the input switch and set the output switch level to realize the closing or opening control of the external relay.

Circuit Design ACEX is a medium-density, cost-effective FPGA for low-end applications, divided into 1K10, 1K30, 1K50 and 1K100, with capacities of 10,000, 30,000, 50,000 and 100,000, respectively, although the capacity is different, but the same Pin compatible in case of package (except in individual cases).

Based on the capacity and I/O quantity requirements, ALTERA's ACEX series EP1K50QC208 was selected. Its rich logic resources and I/O quantity can provide a large number of pulse generation, pulse counting and I/O control functions for the CNC system, simplifying The hardware circuit of the system reduces the power consumption of the system and improves the reliability of the system.

The EP1K50QC208 is a programmable device based on the SRAM process. The configuration data is placed in the SRAM. After the power is turned off, the original logic function of the system will be lost. Therefore, the system must reload the configuration data to the SRAM after power-on again. ALTERA's FPGA configuration methods are: a. Download cable configuration. Generally used in the actual system development and design phase, it will bring a lot of inconvenience to the already designed application system. b. Active configuration mode. No other peripheral controllers are required, and the entire configuration process is booted by the FPGA itself, using dedicated memory to place configuration data. c. Passive configuration. It is not necessary to use ALTERA's dedicated memory, and it can be implemented using inexpensive general-purpose program memory, which can reduce the cost to a certain extent.

In order to protect intellectual property, encryption must be used in critical and core equipment. However, in the above configuration methods, when the system is powered on, the configured bit stream data needs to be written into the FPGA of the SRAM process according to a certain timing. Therefore, a certain circuit is used to sample the data pins of the configuration FPGA, and the configuration is monitored. Bit stream, which can be cloned. Therefore, the encryption problem of the FPGA must be considered in the design to protect the intellectual property.

If you only use the EPC series of dedicated configuration chips or directly use the microprocessor for configuration, you can simplify the peripheral circuits and reduce the configuration cost. However, for the whole CNC system, the configuration is only a part of it. It should be considered from the aspects of system confidentiality, I/O quantity, circuit simplification and system reliability.

This system selects a CPLD chip EPM7128S with 84-pin PLCC package to complete passive serial configuration of FPGA. EPM7128S is the CPLD chip of ALTERA's MAX7000 series. It has a programming encryption bit. When the device is programmed, the encryption bit will be activated, which will make the circuit logic in the EPM7128S chip cannot be read out, thus improving the confidentiality of the system. In addition to the required I/O ports, there are 24 I/Os available for the system; some of the workload can be shared without the need to select a larger FPGA, which reduces the cost to a certain extent. The interface between the CPLD and the FP2GA is as shown. The EPROM needs to be selected according to the size of the accessory. The configuration file size of the ACEX1K50 is 96kB, so the EPROM model selected is M27C1001B.

Software design When the system is initialized, the CPU sends a command to open the configuration to the CPLD. After receiving the command, the CPLD generates a high-to-low transition to the nCONFIG pin. After the nCONFIG signal is raised, nSTATUS will change. Low level, after the CPLD detects this change, it is considered that the FPGA is ready to start configuration. A minimum of 5 μs is required between the first rising edge of the configuration clock and the rising edge of nCONFIG. Since the configuration data is synchronized with the rising edge of the configuration clock, the 1-bit configuration data should be prepared on the data line before the rising edge of the configuration clock, and the configuration data is sent out from the data line in the lower-order first high order. . When all configuration data is sent, the CONF_DONE signal goes high, indicating the end of the configuration. After the CPU detects that CONF_DONE has gone high, the configuration process ends. At this point, DCLK must initialize the device with an extra 10 cycles. During the configuration process, the system needs to perform real-time detection. Once an error occurs, nSTATUS will be pulled low. After the CPLD detects the signal, the nCONFIG signal is pulled low to restart the configuration process. The configuration timing is as shown.

The test results verify that the program written in VHDL language in FPGA is compiled by MAX+PLUSII to generate the configuration file (.sof), and is converted into (.rbf) format and stored in memory M27C1001B. In the system test, after the power-on operation, the configuration data is loaded into the FPGA through the CPLD, and the CPLD monitors the configuration status indication signal of the FPGA, and returns the configuration state to the CPU control end, thereby successfully implementing the configuration of the FPGA. The FPGA receives the data required for fine interpolation from the dual-port RAM, and performs the fine interpolation operation in one interpolation cycle; the pulse signals returned by the opponent wheel and the encoder are counted.

At the same time, external switching control is realized by CPLD and FPGA. Finally, through software and hardware joint debugging, the system realizes four-axis linear interpolation and circular interpolation of any two axes, and the feed rate is uniform and continuous, the interpolation is stable, and the speed is up and down; the radius compensation of the tool can be realized; The system and the computer have the RS232 communication function; the system has a friendly human-machine interface, and the operation menu is displayed in Chinese, which is easy to operate and use.

Conclusion Although the configuration of the FPGA is used in the configuration of the FPGA alone, the cost of configuring the FPGA using the EPC-specific configuration chip or directly using the microprocessor is high. However, from the overall design of the numerical control system, the CPLD is used to encrypt the FPGA of the SRAM process, which overcomes the defect of poor confidentiality of the dedicated configuration chip configuration, and increases the number of general-purpose I/O ports of the numerical control system, and the cost and the use of the microprocessor. The cost of direct configuration is comparable, and the system is more confidential and secure, and simplifies peripheral circuits and improves system integration and reliability.

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