The main controller circuit design can be seen from the above analysis. The improved DCO design is mainly embodied in the internal function circuit implementation of the main controller. The overall circuit and key circuit design of the main controller are described in detail below. The overall circuit structure of the main controller designed by the overall circuit design is as shown.

The dotted line box is the main structure of the controller, INC is the carry control input end, DEC is the borrow control input end, N is the increase/decrease control word input end, CP is the high frequency clock input end, and RESET is the reset input end. The controller output signal is divided by the m divider to obtain the desired frequency signal. The edge detector can sensitively detect the change of the output signal edge (rising edge and falling edge) and output a reset signal to the controller. With the controller to control the entire circuit. The following describes the control principle of the controller in detail according to the three working modes shown: the overall circuit of the main controller (1) Two-way mode When the carry and borrow control inputs are low, the controller works in two points. Frequency mode. Since INC=0 and DEC=0, the two tri-state gates are all off, and the programmable counter is not connected to the JK flip-flop and is in an inactive state. At this time, the N-tube is pulled up so that the J, K input terminal of the JK flip-flop is set to a high level, the JK flip-flop divides the high-frequency clock signal by two, and the controller finally outputs a square wave signal with a duty ratio of 1B4. This frequency signal passes through the m frequency divider and outputs a symmetric square wave signal with a frequency of fs/(2m).

(2) Add pulse mode When the carry control input is high and the borrow control input is low, the controller operates in the add pulse mode. Since INC=1 and DEC=0, the tri-state gate connected to the J terminal of the JK flip-flop is turned on, the output of the variable-program counter is connected to the J terminal of the JK flip-flop, and the K-side is still pulled up to the high level. . The working principle of this mode is: RESET terminal input low level at the beginning, at this time, the programmable counter, JK flip-flop, m frequency divider are reset; when reset becomes high level, the programmable counter starts from 0 Do the counting up, during which the programmable counter output is high, after the tri-state gate is reversed, it is output to the J terminal of the JK flip-flop, so that the JK flip-flop output remains low, and the controller output frequency For fs, when the programmable counter counts the set value N of the control word, it stops counting and outputs a low level, so that the J terminal input of the JK flip-flop becomes a high level, and the JK flip-flop performs a high-frequency clock. The frequency is divided, and when the edge of the DCO's total output signal changes, the edge detector immediately generates a reset signal to the programmable counter, resets it and restarts counting from 0, repeating the above process. It can be seen from the analysis that in each duty cycle (programmable counter reset recount 2 times), the controller adds N pulses to the input pulse signal of the m divider, so that the m divider is advanced by NTs The full number of pulses causes the DCO output signal period to be reduced by NTs.

The DCO is designed based on the working principle of the DCO of the increase/decrease counting type. It has the characteristics of simple structure and easy integration. It greatly adjusts the frequency of the output signal by changing the division ratio of the whole circuit. Its function and function In addition to the N-counting DCO, the DCO concentrates on the advantages of the up/down counting DCO and the N-type counter. When applied to a phase-locked loop, it can achieve the response speed of the N-type counter and its simple structure. Easy to integrate.

(Finish)

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